1. Field of the Invention
The present invention relates to a phase-locked loop circuit that follows the phase of data existing points in a reproduced signal from a partial response (PRS) channel used typically by digital magnetic recording apparatuses.
2. Description of the Prior Art
FIG. 29 is a view of a typical reproduced signal from a PRS (1, -1) channel for magnetic recording; FIG. 30 is a view of a typical reproduced signal from a PRS (1, 0, -1) channel for magnetic recording; FIG. 31 is a view of a typical eye pattern of the reproduced signal from the PRS (1, -1) channel; and FIG. 32 is a view of a typical eye pattern of the reproduced signal from the PRS (1, 0, -1) channel. In FIGS. 29 and 30, each cross (+) symbol indicates a data existing point, i.e., a zero-degree phase. On the PRS (1, 0, -1) and PRS (1, -1) channels for magnetic recording, data exist in zero-degree phases for each ternary level (1, 0 or -1). Where the channel characteristic is properly equalized, signal waveform values converge on one of the three levels (1, 0 or -1) in a zero-degree phase. Thus the optimum way to detect timing information from this waveform is to detect the phase of zero cross points.
However, as is evident from FIGS. 29 through 32, zero cross points exist near phases other than the zero-degree phase (i.e., between zero-degree phases) on the PRS (1, 0, -1) and PRS (1, -1) channels. Take, for example, a clock reproduction circuit such as the one in FIG. 33. The circuit of FIG. 33 comprises a voltage comparator 401 that compares an input signal with a reference voltage, a bidirectional monostable multivibrator circuit 402 located on the output side of the comparator 401, and a phase-locked loop (PLL) circuit 403 of known construction which, located on the output side of the circuit 402, includes a phase comparator 408, a loop filter 408 and a VCO 407, with the clock reproduction circuit of FIG. 33, assume that an attempt is made to compare an input signal with the reference voltage to detect a zero cross phase from the comparison and to input the resulting phase to the PLL circuit for phase synchronization. In that case, as shown in FIG. 34, the monostable multivibrator circuit 402 outputs pulses incorrectly at 180-degree phases. As a result, phase synchronization is disturbed by the zero cross phase information from opposite phases, or the attempt to establish phase synchronization fails in trying to synchronize with negative phases upon the start of the synchronizing operation.